1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device.
2. Description of Related Art
Japanese Patent Application Publication No. 2002-359378 (JP 2002-359378 A) describes a method for manufacturing a MOSFET including a floating p-layer around a bottom portion of a trench, by use of a semiconductor substrate made from silicon carbide. In a case where the semiconductor substrate made from silicon carbide is used, impurity is hard to diffuse in the semiconductor substrate, in comparison with a case where a semiconductor substrate made from silicon is used. Particularly, in a case where impurity is hard to diffuse in a direction perpendicular to an injection direction of impurity ions in a semiconductor substrate and the impurity ions are injected into a bottom portion of a trench to form a floating layer, the impurity ions thus injected are hard to diffuse in a plane direction of the semiconductor substrate. As a result, when a width of the floating layer in a short direction of a trench gate (a direction perpendicular to a longitudinal direction of the trench gate) is insufficient, a withstand voltage of a semiconductor device decreases. In the manufacturing method of JP 2002-359378 A, in a step of forming the floating p-layer, boron ions that are relatively easy to diffuse are injected in a deeper position of the semiconductor substrate, and aluminum ions that are relatively hard to diffuse are injected in a shallower position. Hereby, the width of the floating p-layer in a horizontal direction is widened in a deep position of the semiconductor substrate, but is narrowed in a shallow position.